The present invention relates to a semiconductor memory device having redundant memory cells and, more particularly, to a technology for reading out data at a high speed from the redundant memory cells, namely, a technology which is effective if applied to a static or dynamic RAM (i.e., Random Access Memory) or a single chip microcomputer including such RAM.
The technology of the prior art for reading out data at a high speed from the redundant memory cells is disclosed in Japanese Patent Laid-Open No. 21500/1990. According to this prior art, a word line included in one memory mat is selected together with a redundant memory cell of another memory mat adjoining the former, and a sense amplifier at said another memory mat including the redundant memory cell is activated, if the access address at this time is to a defective cell, whereas the sense amplifier at said one memory mat is activated if the access address is not to a defective cell. Thus, the data read from the redundant memory cell is speeded up by selecting the redundant memory cell without awaiting the result of decision of necessity for the redundant saving of the access address and by handling the conflict between the necessary and unnecessary read data with a selective activation of the sense amplifier.
Here, the prior art has a word line structure called the "divided word line structure". This structure has a common main word line shared among a plurality of memory mats and a plurality of sub word lines intrinsic to the individual memory mats. The main word line transmits a word line select signal commonly to the plurality of memory mats. The sub word lines are drive by a sub word driver which is made receptive of a transmission signal of the main word line and a control signal for outputting a drive signal. According to the prior art, therefore, the word lines to be selected simultaneously by the individual adjoining memory mats are the sub word lines and the corresponding main word line.
In the prior art, however, our investigations have found out that there is a large delay in the timing for selecting the main word line at the redundant memory cell, as will be described in the following. The sub word lines arranged at each memory mat are not driven to their select level till the select signal from the main word line is transmitted to the sub word driver. At this time, the main word line for feeding the select signal commonly to the individual memory mats has a larger wiring length than that of the sub word lines so that it forms a relatively high undesired delay component with the capacity and/or resistance components parasitic thereto. In order to drive the redundant main word line and the sub word lines for the redundant memory cells to the select level, moreover, whether or not the access address is to a defective cell to be redundantly replaced has to be decided through a logic of a redundant program circuit or the like. As compared with the case of selecting memory cells included in one memory mat, the timing for selecting the redundant memory cells in the adjoining memory mat is delayed by the rise of the main word line for the redundant selection so that an identically fast access cannot be warranted for the products with and without redundant memory cells.